A Thermal Evaluation of Integrated Circuits: on Chip Offset Temperature Measurement and Modeling

This paper presents a chip and test configuration for thermal evaluation based on MOSIS 0.5μ technology. We measured spatial temperature differences as high as 20.65°C on a 2mm by 2mm Tiny Chip. Our research shows that circuit location on a chip determines its default offset temperature and heat transport properties, which must be considered for prediction of junction temperature and electro-thermal analysis. A model has been developed to verify measurement results. The results yield insight about on-chip heat dissipation, which is very useful for mixed-signal VLSI designs and circuit reliability analysis.